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LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER
ICS83210
GENERAL DESCRIPTION
The ICS83210 is a low skew, 1-to-10 HSTL Fanout IC S Buffer and a member of the HiPerClockSTM Family HiPerClockSTM of High Performance Clock Solutions from IDT. The class II HSTL outputs are balanced push-pull in design, capable of delivering 16mA into a 10pF load. This class allows both source series termination and symmetrically double parallel termination.
FEATURES
* Ten single-ended HSTL outputs * One single-ended HSTL clock input * Maximum input frequency: 150MHz * Output skew: 110ps (maximum) * Part-to-part skew: 2ns (maximum) * 1.5V power supply * 0C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
BLOCK DIAGRAM
Q0 Q1 IN Q8 Q9 nOE Pulldown
PIN ASSIGNMENT
GND
32 31 30 29 28 27 26 25 VDD GND VDD nOE GND IN VDD GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GND GND Q9 VDD VDD Q8 Q7 GND
32-Lead TQFP 7mm x 7mm x 1.0mm package body Y package Top View
GND
GND
VDD
VDD
ICS83210
Q0
Q1
Q2
24 23 22 21 20 19 18 17
GND Q3 Q4 VDD VDD Q5 Q6 GND
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TABLE 1. PIN DESCRIPTIONS
Number 1, 3, 7, 12, 13, 20, 21, 28, 29 2, 5, 8, 9, 10, 16, 17, 24, 25, 31, 32 4 Name VDD GND Power Power Type Description Power supply pins. Power supply ground. Output enable/disable input pin. When LOW, outputs Qx outputs Pulldown are enabled. When HIGH, Qx outputs are disabled low. LVCMOS/LVTTL interface levels. Single-ended reference clock input. HSTL interface levels.
nO E
Input
5 IN Input Q9, Q8, Q7, 11, 14, 15, Q6, Q5, Q4, Output Single-ended HSTL clock outputs. 18, 19, 22, 23, 26, 27, 30 Q3, Q2, Q1, Q0 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN COUT ROUT Parameter Input Capacitance Input Pulldown Resistor Output Pin Capacitance Output Impedance Test Conditions Minimum Typical 4 51 4.5 20 6 Maximum Units pF k pF
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 75.5C/W (0 mps)
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 1.5V 8%, TA = 0C TO 85C
Symbol VDD IDD IDDQ Parameter Power Supply Voltage Power Supply Current Quiescent Supply Current Outputs Loaded @ 62.5MHz VIN = 0V, outputs disabled Test Conditions Minimum 1.38 Typical 1.5 215 Maximum 1.62 250 1 Units V mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 1.5V 8%, TA = 0C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current nOE nOE nOE nOE -5 Test Conditions Minimum 0.7*VDD -0.3 Typical Maximum VDD + 0.3 0.3*VDD 150 Units V V A A
TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 1.5V 8%, TA = 0C TO 85C
Symbol Parameter VIH VIL VOH VOL Input High Voltage Input Low Voltage IN IN Test Conditions VREF = 0.75V IOH = -16mA IOL = 16mA Minimum 0.85 -0.3 1.0 -0.3 Typical Maximum 1.8 0.65 VDD + 0.3 0.4 Units V V V V
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to ground.
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TABLE 4. AC CHARACTERISTICS, VDD = 1.5V 8%, TA = 0C TO 85C
Symbol fIN tPLH tPHL tsk(o) tsk(pp) tEN tDIS t R / tF o dc Parameter Input Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Enable Time Output Disable Time Output Rise/Fall Time Output Duty Cycle 20% to 80% Fout 100MHz 250 48 Test Conditions Minimum Typical Maximum 150 1.0 1.0 5. 5 5.5 110 2 7 7 1.3 52 55 Units MHz ns ns ps ns ns ns ns % %
Fout > 100MHz 45 NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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PARAMETER MEASUREMENT INFORMATION
0.75V8% PART 1 VDD
SCOPE
Qx
Qx
V
DD
2
PART 2
V
DD
HSTL
GND
Qy
2 tsk(pp)
-0.75V8%
1.5V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
V
Qx
DD
VDD
VDD 2 VDD VDD 2 tpHL
2
IN
2
V
Qy
Q0:Q9
DD
2 tsk(o)
2 tpLH
OUTPUT SKEW
PROPAGATION DELAY
V
DD
80% 20% tR
80% 20% tF
Q0:Q9
2
t PW
t
PERIOD
Clock Outputs
odc =
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS:
HSTL OUTPUTS All unused HSTL outputs can be left floating. We recommend that there is no trace attached.
RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE
FOR
32 LEAD TQFP
by Velocity (Meters per Second)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards 75.5C/W
1
65.8C/W
2.5
62.2C/W
TRANSISTOR COUNT
The transistor count for ICS83210 is: 218 Pin compatible with CY2HH8110
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PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP
-HD VERSION HEAT SLUG DOWN
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS ABA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 0.95 0.30 0.09 MINIMUM NOMINAL 32 -0.10 1.0 0.35 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.20 0.15 1.05 0.40 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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TABLE 7. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS83210AY ICS83210AY 32 lead TQFP tray 0C to 85C ICS83210AYT ICS83210AY 32 lead TQFP 1000 tape & reel 0C to 85C ICS83210AYLF ICS83210AYLF 32 lead "Lead-Free" TQFP tray 0C to 85C ICS83210AYLFT ICS83210AYLF 32 lead "Lead-Free" TQFP 1000 tape & reel 0C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
netcom@idt.com 480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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